Current and emerging networks move increasingly diverse traffic types. Such traffic types are also referred to herein as services. In the past, network equipment was dominated by a few traffic types such as time division multiplexed (TDM) or asynchronous transfer mode (ATM). As network applications have expanded, new traffic types such as Internet protocol (IP) must be supported, particularly for equipment at the edge of the network. Since legacy services are still present, networks need to handle multiple services. Such an environment requires multiservice network equipment. It is desirable for cost and other reasons to implement multiservice equipment with devices that can handle multiple services as opposed to using a dedicated device for each service. This multiservice environment therefore requires physical layer and link layer devices that can process multiple services.
A network processor is one example of what is more generally referred to herein as a link layer device, where the term “link layer” generally denotes a switching function layer, also referred to as the data link layer in the well-known Open Systems Interconnection (OSI) model. Network processors and other link layer devices are commonly used to implement processing associated with various packet-based and cell-based protocols, such as, for example, IP and ATM.
Communication between a physical layer device and a network processor or other type of link layer device may be implemented in accordance with an interface standard, such as the SPI-3 interface standard described in Implementation Agreement OIF-SPI3-01.0, “System Packet Interface Level 3 (SPI-3): OC-48 System Interface for Physical and Link Layer Devices,” Optical Internetworking Forum, 2001, which is incorporated by reference herein. Another example of a known interface standard is the POS-2 standard described in POS-PHY Saturn Compatible Packet Over SONET Interface Specification for Physical Layer Devices, PMC-Sierra, Inc., PMC-971147, Issue 5, 1998, also incorporated by reference herein.
A given physical layer device may comprise a multiple-port device which communicates over multiple channels with the link layer device. Such communication channels, also commonly known as MPHYs, may be viewed as examples of what are more generally referred to herein as physical layer device ports. A given set of MPHYs that are coupled to a link layer device may comprise multiple ports associated with a single physical layer device, multiple ports each associated with one of a plurality of different physical layer devices, or combinations of such arrangements. As is well known, a link layer device may be advantageously configured to detect backpressure for a particular MPHY via polling of the corresponding MPHY address on its associated physical layer device. The detected backpressure is used by the link layer device to provide flow control and other traffic management functions, thereby improving link utilization.
The above-noted interface standards generally specify techniques for addressing an MPHY and for moving payload data over the interface. The addressing may use the same or separate pins from the payload. For the 8-bit mode of the SPI-3 standard, the MPHY address uses eight payload pins and thus the maximum number of MPHYs that can be specified is 28=256. This maximum is based on the bus width of the 8-bit SPI-3 mode and cannot be increased without breaking compliance with this mode. For the POS-2 standard, the MPHY address uses pins separate from the payload, and the maximum number of MPHYs that can be specified is 31. There are well-known extensions to the POS-2 standard that increase the maximum number of MPHYs in increments of 31 by using additional pins. However, the number of pins becomes unmanageable when the MPHY number is scaled to 1024 or more, although such a number of MPHYs is readily achievable in physical layer devices using current integrated circuit technology.
It may also be desirable to exchange non-payload information other than an MPHY address between the physical layer device and the link layer device. Such other information may be transmitted using so-called “in-band” techniques so as to avoid significantly reducing the bandwidth allocated to true payload traffic.
The primary disadvantage of using the conventional SPI-3 or POS-2 standards is that the number of MPHYs that can be addressed without a significant increase in pins is much smaller than that which can now be achieved in physical layer devices. Increasing the number of pins increases package cost and power for both the link layer device and the physical layer device. Compatibility with the standards may also be compromised if additional pins are required. It is desirable to maintain compatibility with the standards so that both low MPHY count and high MPHY count applications may be supported with the same physical layer device.
It should be noted that a multiservice environment may impose other requirements in addition to support of a large number of MPHYs. For example, it may be desirable to allow the link layer device to start a low priority packet on one MPHY, then interrupt this packet to send a higher priority cell on a different MPHY, and then resume the lower priority packet without having to resend its addressing information. This is referred to as interleaving MPHYs, and is particularly useful in a multiservice application to control latency for cells. To support interleaving MPHYs, the physical layer device must save the MPHY address and other non-payload information for the low priority packet and restore it when the high priority cell ends. In general, this can be several bytes of state per MPHY, a significant amount of on-chip memory for devices with thousands of MPHYs. Storage of state per MPHY is not required if the physical layer device supports only non-interleaving MPHYs. For non-interleaving MPHYs, the interface can only switch to a different MPHY on a packet or cell boundary. Physical layer devices with a conventional flat MPHY numbering scheme must then trade off either high cost to store interleaving state or jeopardize services like ATM by imposing a potentially large and variable latency when sharing the physical layer device with an IP service.
A proprietary interface which is not compatible with the above-noted SPI-3 and POS-2 standards but supports a larger number of MPHYs is known as ANY-PHY. Various aspects of the ANY-PHY interface are described in U.S. Pat. No. 6,671,758, assigned to PMC-Sierra, Inc. and entitled “Bus Interface for Cell and/or Packet Data Transfer.” This interface uses two bytes of the payload for MPHY addressing. These bytes are referred to as prepend bytes, and support addressing of 216=65,536 MPHYs. Although this approach easily supports 1024 or more MPHYs, it is not compliant with the SPI-3 and POS-2 standards, and uses a flat MPHY numbering scheme. Implementations may require a large amount of on-chip memory solely for the link layer interface. Due to the flat MPHY numbering scheme, ANY-PHY cannot group MPHYs according to service. In addition, a given implementation is likely to restrict interleaving to reduce the on-chip memory required to store interleave state for up to 65,536 MPHYs. For example, if an implementation of the ANY-PHY interface followed the recommendation of the SPI-3 standard, each of the 65,536 MPHYs would include 256 bytes of memory for a payload FIFO. This is a total of 16 Mbytes of memory for each direction of the interface, which would likely be considered too large for a cost-effective chip implementation, particularly if the chip is a non-DRAM chip. The required memory could be reduced by storing only minimal configuration and state information for each MPHY, but even with a modest four bytes per MPHY the interface would require 256 Kbytes of memory for each direction. Given these memory requirements, it is unlikely that any practical ANY-PHY implementation would attempt to support all 65,536 MPHYs.
Even with a smaller number of MPHYs, dedicating two bytes of the payload to MPHY addressing substantially reduces the bandwidth available to the actual payload. For example, when sending 53-byte ATM cells over an 8-bit ANY-PHY interface, the prepend bytes represent a 3.8% bandwidth penalty. Furthermore, since the prepend bytes carry only address information, other in-band information also subtracts from available payload bandwidth. For example, some packet protocols, such as Point-to-Point Protocol (PPP), require priority information (e.g., a 2 to 4 bit class) to be associated with each packet. For ANY-PHY, the packet class must be transferred as part of the payload. The ANY-PHY specification includes address pins separate from the payload pins as does the POS-2 standard. Unlike POS-2, ANY-PHY uses these separate address pins solely for polling the FIFO status whereas POS-2 uses them for both MPHY selection and polling. Thus, the ANY-PHY interface sacrifices additional bandwidth by duplicating the address information on the payload pins.
It is therefore apparent that a need exists for an improved interface between a physical layer device and a link layer device, which is able to support a large number of MPHYs in a multiservice environment while maintaining compliance with one or more standards and avoiding problems such as the above-described excessive memory requirements and bandwidth reduction.